Cirrus Logic CS42L56 - Manual (Page 30)

30 DS851F2
CS42L56
4. APPLICATIONS
4.1 Overview
4.1.1 Basic Architecture
The CS42L56 is a highly integrated, ultra-low power, 24-bit audio CODEC comprised of stereo A/D and
D/A converters with pseudo-differential stereo input and output amplifiers. The ADC and DAC are de-
signed using multi-bit delta-sigma techniques; both converters operate at a low oversampling ratio of
64xFs, maximizing power savings while maintaining high performance. The CODEC accepts and is ca-
pable of generating serial audio clocks (SCLK, LRCK) derived from a USB or a standard audio input Mas-
ter Clock (MCLK). Designed with a very low voltage digital core and low voltage Class H amplifiers
(powered from an integrated low-dropout regulator and a step-down/inverting charge pump, respectively),
the CS42L56 provides significant reduction in overall power consumption.
4.1.2 Line Inputs
The analog input portion of the CODEC allows selection from up to three stereo line-level sources into a
Programmable Gain Amplifier (PGA). The optional line pseudo-differential configuration provides com-
mon-mode noise rejection for single-ended inputs and is available on AIN1x or AIN2x. If pseudo-differen-
tial operation is not required, the pins can also be configured independently as two additional analog
inputs (AIN3x).
4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers)
The analog output portion of the CODEC includes separate pseudo-differential headphone and line out
Class H amplifiers. An on-chip step-down/inverting charge pump creates a positive and negative voltage
equal to the input or one-half the input supply for the amplifiers, allowing an adaptable, full-scale output
swing centered around ground. The inverting architecture eliminates the need for large DC-blocking ca-
pacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages. The
step-down architecture allows the amplifier’s power supply to adapt to the required output signal. This
adaptive power supply scheme converts traditional Class AB amplifiers into more power-efficient Class H
amplifiers.
4.1.4 Fixed-function DSP Engine
The fixed function digital signal processing engine processes both the PCM serial input data and ADC
output data allowing a mix between the two. Independent volume control, left/right channel swaps, mono
mixes, tone control comprise the DSP engine.
4.1.5 Beep Generator
The beep generator delivers tones at select frequencies across approximately two octave major scales.
With independent volume control, beeps may be configured to occur continuously, periodically or at single
time intervals.
4.1.6 Power Management
Several control registers and bits provide independent power down control of the ADC, PGA, DSP, head-
phone and line outputs, allowing operation in select applications with minimal power consumption.