2 power-down sequence, Cs42l56 – Cirrus Logic CS42L56 User Manual

Page 50

DS851F2

CS42L56

4. Wait a minimum of 500 ns before writing to the control port.
5. The default state of the master power down bit, PDN, is 1b. Load the following register settings while

keeping the PDN bit set to 1b.

6. Configure the headphone and line power down controls for ON, OFF, or HPDETECT operation.

Register Controls: PDN_HPx[1:0], PDN_LINx[1:0]

7. Configure the serial port I/O control for master or slave operation.

Register Controls: M/S

8. Configure the master clock (MCLK) and bit clock (SCLK) I/O control as desired. Refer to

4.8 “Serial

Port Clocking” on page 47

for the required configuration for a given master clock.

Register Controls: MKPREDIV, MCLKDIV2, SCLK=MCLK

9. Configure the sample rate (LRCK) controls for the desired sample rate. Refer to

4.8 “Serial Port

Clocking” on page 47

for the required configuration for a given sample rate.

Register Controls: See Register 05h

10. The default state of the DSP engine’s power down bit, PDN_DSP, is 0b. It is not necessary to power

down the DSP before changing the various DSP functions. The DSP may be powered down for
additional power savings.

11. To minimize pops on the headphone or line amplifier, each respective analog volume control must

first be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]

12. After muting the headphone or line amplifiers, set the PDN bit to 0b.
13. Wait 75 ms for the headphone or line amplifier to power up.
14. Un-mute and ramp the volume for the headphone or line amplifiers to the desired level.
15. Bring RESET low if the analog or digital supplies drop below the recommended operating condition

to prevent power glitch related issues.

4.11.2 Power-Down Sequence

1. To minimize pops during volume transitions, mute the master volume with soft ramp enabled.

Register Controls: MSTxMUTE, DIGSFT

2. The required wait time for muting the master volume as described in

above depends on the soft

ramp rate, initial master volume setting and sample rate. For example, if the master volume is set to
0 dB and the sample rate is 48 kHz, the required wait time is at least:
8 [soft ramp rate is 1/8 dB per LRCK] x 102 [volume must transition from 0 dB to -102 dB] x 21 µs
[period of 48 kHz LRCK] = 17 ms. Wait at least [the delay required according to the details in this
step].

3. To minimize pops on the headphone or line amplifier, each respective analog volume control must

first be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]

4. Disable soft ramp and zero cross volume transitions.

Register Controls: ANLGSFT, ANLGZC, DIGSFT

5. Set the PDN bit to ‘1’b.
6. Wait at least 100 µs.

Power Up Sequence

Step

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Step

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Steps

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