Cirrus Logic CS42L56 - Manual (Page 64)

64 DS851F2
CS42L56
6.10 Status (Address 0Ah) (Read Only)
Bits [6:0] in this register are “sticky”. 1b means the associated error condition has occurred at least once
since the register was last read. 0b means the associated error condition has NOT occurred since the last
reading of the register. Reading the register resets these bits to 0. Bit 7 is not “sticky” and will always indicate
current status when the register is read.
6.10.1 HPDETECT Pin Status (Read Only)
Indicates the status of the HPDETECT pin.
6.10.2 Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
Note: On initial power up and application of clocks, this bit will report 1b as the serial port re-synchro-
nizes.
6.10.3 DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
6.10.4 MIXx Overflow (Read Only)
Indicates the over-range status in the PCM mix data path.
6.10.5 ADCx Overflow (Read Only)
Indicates the over-range status in the ADC signal path.
7 6 5 4 3 2 1 0
HPDETECT SPCLKERR DSPBOVFL DSPAOVFL MIXBOVFL MIXAOVFL ADCBOVFL ADCAOVFL
HPDETECT Pin State
0 Low
1 High
SPCLKERR Serial Port Clock Status:
0 MCLK/LRCK ratio is valid.
1 MCLK/LRCK ratio is not valid.
Application: “Serial Port Clocking” on page 47
DSPxOVFL DSP Overflow Status:
0 No digital clipping has occurred in the data path after the DSP.
1 Digital clipping has occurred in the data path after the DSP.
MIXxOVFL PCM Overflow Status:
0 No digital clipping has occurred in the data path of the ADC and PCM mix of the DSP.
1 Digital clipping has occurred in the data path of the ADC and PCM mix of the DSP.
ADCxOVFL ADC Overflow Status:
0 No clipping has occurred anywhere in the ADC signal path.
1 Clipping has occurred in the ADC signal path.