Cirrus Logic CS42L56 - Manual (Page 47)

DS851F2 47
CS42L56
24.0000
(MKPREDIV=1b)
(MCLKDIV2=1b)
8.0000 3000 0.496 ~48 11101
11.0294 2176 0.75 32 11011
12.0000 2000 0.744 ~32 11001
16.0000 1500 0.992 ~24 10101
22.0588 1088 1.500 16 10011
24.0000 1000 1.488 ~16 10001
32.0000 750 1.984 ~12 01101
44.1180 544 3.000 8 01011
48.0000 500 2.976 ~8 01001
12.0000
(MKPREDIV=0b)
(MCLKDIV2=1b)
8.0000 1500 0.496 ~24 11101
11.0294 1088 0.75 16 11011
12.0000 1000 0.744 ~16 11001
16.0000 750 0.992 ~12 10101
22.0588 544 1.500 8 10011
24.0000 500 1.488 ~8 10001
32.0000 375 1.984 ~6 01101
44.1180 272 3.000 4 01011
48.0000 250 2.976 ~4 01001
6.0000
(MKPREDIV=0b)
(MCLKDIV2=0b)
8.0000 750 0.496 ~12 11101
11.0294 544 0.75 8 11011
12.0000 500 0.744 ~8 11001
16.0000 375 0.992 ~6 10101
22.0588 272 1.500 4 10011
24.0000 250 1.488 ~4 10001
32.0000 187.5 1.984 ~3 01101
44.1180 136 3.000 2 01011
48.0000 125 2.976 ~2 01001
24.5760
(MKPREDIV=1b)
(MCLKDIV2=1b)
8.0000 3072 0.512 48 11100
12.0000 2048 0.768 32 11000
16.0000 1536 1.024 24 10100
24.0000 1024 1.536 16 10000
32.0000 768 2.048 12 01100
48.0000 512 3.072 8 01000
12.2880
(MKPREDIV=0b)
(MCLKDIV2=1b)
8.0000 1536 0.512 24 11100
12.0000 1024 0.768 16 11000
16.0000 768 1.024 12 10100
24.0000 512 1.536 8 10000
32.0000 384 2.048 6 01100
48.0000 256 3.072 4 01000
6.1440
(MKPREDIV=0b)
(MCLKDIV2=0b)
8.0000 768 0.512 12 11100
12.0000 512 0.768 8 11000
16.0000 384 1.024 6 10100
24.0000 256 1.536 4 10000
32.0000 192 2.048 3 01100
48.0000 128 3.072 2 01000
MCLK (MHz) LRCK (kHz)
MCLK/ LRCK
Clock Ratio
SCLK (MHz)
MCLK/SCLK
Clock Ratio
RATIO[4:0]
Table 3. Serial Port Clock Ratio Settings (Continued)