Cirrus Logic CS42L56 - Manual (Page 51)

DS851F2 51
CS42L56
The CODEC will be fully powered down after this 100 µs delay. Prior to the removal of the master
clock (MCLK), this delay of at least 100 µs must be implemented after step
5 to avoid premature
disruption of the CODEC’s power down sequence. A disruption in the CODEC’s power down
sequence may abruptly stop the charge pump, causing the headphone and/or line amplifiers to drive
the outputs up to the VCP supply. Such disruption may also cause clicks and pops on the output of
the DAC’s.
7. Optionally, MCLK may be removed at this time.
8. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
reset to their default state.
9. Power Supply Removal (Option 1): Switch power supplies to a high impedance state. Note: VCP
must be removed prior to VA to maintain the relationship specified in “Recommended Operating
Conditions” on page 14 .
10. Power Supply Removal (Option2): To minimize pops when the power supplies are pulled to ground,
a discharge resistor must be added in parallel with the capacitor on the FILT+ pin. With a 1 M 
resistor and a 2.2 µF capacitor on FILT+, FILT+ will ramp to ground in approximately 5 seconds.
After step 5 , wait the required time for FILT+ to ramp to ground before pulling VA to ground. Note:
VCP must be pulled to ground prior to VA to maintain the relationship specified in “Recommended
Operating Conditions” on page 14 .
4.12 Recommended PGA to HP or Line Power Sequence (Analog Passthrough)
4.12.1 Power-Up Sequence
1. Hold RESET low until the power supplies are stable. Note: VA must be applied prior to VCP to
maintain the relationship specified in “Recommended Operating Conditions” on page 14 . RESET
should be held low for a minimum of 1 ms after power supplies are stable.
2. Apply MCLK at the appropriate frequency.
3. Bring RESET high.
4. Wait a minimum of 500 ns before writing to the control port.
5. The default state of the master power down bit, PDN, is ‘1’b. Load the following register settings while
keeping the PDN bit set to ‘1’b.
6. Configure the headphone and line power down controls for ON, OFF, or HPDETECT operation.
Register Controls: PDN_HPx[1:0], PDN_LINx[1:0]
7. Configure the HP and/or Line amplifiers to receive the analog output from the PGA.
Register Controls: LINExMUX, HPxMUX
8. Power down the DSP engine.
Register Controls: PDN_DSP
9. To minimize pops on the headphone or line amplifier, each respective analog volume control must
first be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]
10. After muting the headphone and/or line amplifiers, set the PDN bit to ‘0’b.
11. Wait 75 ms for the headphone or line amplifier to power up.
12. Un-mute and ramp the volume for the headphone or line amplifiers to the desired level.
Power Down Sequence Register Location
Step 1 a ................................
Step 1 b ................................
Step 4 ..................................
Step 5 ..................................
“Headphone Volume Control” on page 84 , “Line Volume Control” on page 84
“Headphone Channel x Mute” on page 83 , “Line Channel x Mute” on page 84
“Analog Soft Ramp” on page 64 , “Analog Zero Cross” on page 64 , “Digital Soft Ramp” on page 64
“Power Down” on page 59