Cirrus Logic CS42L56 - Manual (Page 87)

DS851F2 87
CS42L56
7. PCB LAYOUT CONSIDERATIONS
7.1 Power Supply
As with any high-resolution converter, the CS42L56 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized.
Figure 1 on page 11 shows the recommend-
ed power arrangements, with VA and VCP connected to clean supplies. VLDO, which powers the digital
circuitry, may be run from the system logic supply. Alternatively, VLDO may be powered from the analog
supply via a ferrite bead. In this case, no additional devices should be powered from VLDO.
7.2 Grounding
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS42L56 as pos-
sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS42L56 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+,
VQ, +VHPFILT and -VHPFILT capacitors must be positioned to minimize the electrical path from each re-
spective pin to AGND. The CDB42L56 evaluation board demonstrates the optimum layout and power sup-
ply arrangements.
7.3 QFN Thermal Pad
The CS42L56 comes in a compact QFN package. The under side of the QFN package reveals a large metal
pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an
equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias
should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split
ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The
CDB42L56 evaluation board demonstrates the optimum thermal pad and via configuration.