Intel 815 - Manual (Page 92)

AGP/Display Cache Design Guidelines
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92 Intel
®
815 Chipset Platform Design Guide
7.4.4 AGP Clock Routing
The maximum total AGP clock skew, between the GMCH and the graphics component, is 1 ns for
all data transfer modes. This 1 ns includes skew and jitter that originates on the motherboard and
clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all
points on the clock edge that fall within the switching range.
For AGP clock routing guidelines for the Intel 815 chipset platform, refer to Section 11.3.
7.4.5 AGP Signal Noise Decoupling Guidelines
The following routing guidelines are recommended for the optimal system design. The main focus
of these guidelines is to minimize signal integrity problems on the AGP interface of the GMCH.
The following guidelines are not intended to replace thorough system validation for products
based on the Intel 815 chipset platform.
•
A minimum of six 0.01
µ
F capacitors are required and must be as close as possible to the
GMCH. These should be placed within 70 mils of the outer row of balls on the GMCH for
VDDQ decoupling. The closer the placement, the better.
•
The designer should evenly distribute placement of decoupling capacitors in the AGP
interface signal field.
•
It is recommended that the designer use a low-ESL ceramic capacitor, such as with a 0603
body-type X7R dielectric.
•
To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the
trace spacing may be reduced as the traces go around each capacitor. The narrowing of space
between traces should be minimal and for as short a distance as possible (1 inch maximum).
•
In addition to the minimum decoupling capacitors, the designer should place bypass
capacitors at vias that transition the AGP signal from one reference signal plane to another.
On a typical four-layer PCB design, the signals transition from one side of the board to the
other. One extra 0.01
µ
F capacitor is required per ten vias. The capacitor should be placed as
close as possible to the center of the via field.
7.4.6 AGP Routing Ground Reference
It is strongly recommended that at least the following critical signals be referenced to ground from
the GMCH to an AGP video controller on an AGP-only motherboard, using a minimum number of
vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#,
G_GTRY#, G_IRDY#, G_GNT#, and ST[2:0].
In addition to the minimum signal set listed previously, it is strongly recommended that half of all
AGP signals be referenced to ground, depending on the board layout. In an ideal design, the
complete AGP interface signal field would be referenced to ground. This recommendation is not
specific to any particular PCB stack-up, but should be applied to all designs using the Intel 815
chipset platform.