Intel 815 - Manual (Page 91)

AGP/Display Cache Design Guidelines
R
Intel
®
815 Chipset Platform Design Guide 91
Figure 1. AGP Down 2X/4X Routing Recommendations
AGP_Down_1x-2x
AGP Compliant
Graphics Device
Length: 0.5" - 6.0" Width to
spacing: 1:3 Strobe-to-Data
Mismatch: ±0.5"
Signals
Strobes
Intel®
82815
Length: Dependent on Data
Width: 5 mil
Spacing: 15 mils
Strobe-to-Strobe Mismatch: ±0.2"
7.4.3 AGP Routing Guideline Considerations and Summary
This section applies to all AGP signals, as follows:
•
The 2X/4X timing domain signals can be routed with 5-mil spacing, when breaking out of the
GMCH. The routing must widen to the documented requirements, within 0.3 of the GMCH
package.
•
When matching the trace length for the AGP 4X interface, all traces should be matched from
the ball of the GMCH to the ball on the AGP compliant device. It is not necessary to
compensate for the lengths of the AGP signals on the GMCH package.
•
Reduce line length mismatch to ensure added margin. Trace length mismatch for all signals
within a signal group should be as close to zero as possible, to provide timing margin.
•
To reduce trace-to-trace coupling (cross-talk), separate the traces as much as possible.
•
All signals in a signal group should be routed on the same layer.
•
The trace length and trace spacing requirements must not be violated by any signal.
Table 23. AGP 2.0 Routing Summary
Signal
Max.
Length
Trace Spacing
(5-mil Traces)
Length
Mismatch
Relative to Notes
1X Timing
Domain 7.5” 5 mils No
requirement N/A None
2X/4X Timing
Domain Set 1 6” 15 mils 1 ±0.5” AD_STB0
and
AD_STB0#
AD_STB0,
AD_STB0# must be
the same length
2X/4X Timing
Domain Set 2 6” 15 mils 1 ±0.5” AD_STB1
and
AD_STB1#
AD_STB1,
AD_STB1# must be
the same length
2X/4X Timing
Domain Set 3 6” 15 mils 1 ±0.5” SB_STB
and
SB_STB#
SB_STB, SB_STB#
must be the same
length
NOTES:
1. Each strobe pair must be separated from other signals by at least 20 mils.