Intel 815 - Manual (Page 137)

Clocking
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Intel
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815 Chipset Platform Design Guide 137
11.4 Clock Decoupling
Several general layout guidelines should be followed when laying out the power planes for the
Intel CK-815 clock generator.
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Isolate the power plane to each clock group.
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Place local decoupling as close as possible to power pins and connect with short, wide traces
and copper.
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Connect pins to the appropriate power plane with power vias (larger than signal vias).
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Bulk decoupling should be connected to plane with 2 or more power vias.
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Minimize clock signal routing over plane splits.
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Do not route any signals underneath the clock generator on the component side of the board.
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An example signal via is a 14-mil finished hole with a 24-mil to 26-mil path. An example
power via is an 18-mil finished hole with a 33-mil to 38-mil path. For large decoupling or
power planes with large current transients, a larger power via is recommended
11.5 Clock Driver Frequency Strapping
An Intel CK-815-compliant clock driver device uses two of its pins to determine whether
processor clock outputs should run at 133 MHz, 100 MHz, or 66 MHz. The pin names are SEL0
and REF0. In addition, a third strapping pin is defined (SEL1) that must be pulled high for normal
clock driver operation. Refer to the appropriate Intel CK-815 clock driver specification for
detailed strap timings and the logic encoding of straps.
SEL0 and REF0 are driven by either the processor, which depends on the processor populated in
the 370-pin socket, or pull-up resistors on the motherboard. While SEL0 is a pure input to a
Intel CK-815-compliant clock driver, REF0 is also the 14 MHz output that drives the ICH and
other devices on the platform. In addition to sampling BSEL[1:0] at reset, Intel CK-815-compliant
clock drivers are configured by the BIOS via a two-wire interface to drive SDRAM clock outputs
at either 100 MHz (default) or 133 MHz (if all system requirements are met).