Intel 815 - Manual (Page 9)

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Intel
®
815 Chipset Platform Design Guide 9
Figure 49. Schematic of RAMDAC Video Interface.........................................................102
Figure 50. Cross-Sectional View of a Four-Layer Board .................................................103
Figure 51. Recommended RAMDAC Component Placement & Routing........................104
Figure 52. Recommended RAMDAC Reference Resistor Placement and Connections 105
Figure 53. Hub Interface Signal Routing Example ..........................................................107
Figure 54. Single-Hub-Interface Reference Divider Circuit .............................................109
Figure 55. Locally Generated Hub Interface Reference Dividers ....................................109
Figure 56. IDE Minimum/Maximum Routing and Cable Lengths ....................................112
Figure 57. Ultra ATA/66 Cable.........................................................................................112
Figure 58. Host-Side IDE Cable Detection ......................................................................114
Figure 59. Drive-Side IDE Cable Detection .....................................................................115
Figure 60. Resistor Schematic for Primary IDE Connectors ...........................................116
Figure 61. Resistor Schematic for Secondary IDE Connectors.......................................117
Figure 62. Flexible IDE Cable Detection..........................................................................118
Figure 63. Recommended USB Schematic.....................................................................123
Figure 64. PCI Bus Layout Example for Four PCI Connectors .......................................124
Figure 65. External Circuitry of RTC Oscillator................................................................126
Figure 66. Diode Circuit to Connect RTC External Battery..............................................127
Figure 67. RTCRESET External Circuit for the ICH RTC................................................128
Figure 68. Platform Clock Architecture (2 DIMMs)..........................................................132
Figure 69. Universal Platform Clock Architecture (3 DIMMs)..........................................134
Figure 70. Clock Routing Topologies ..............................................................................135
Figure 71. Power Delivery Map........................................................................................142
Figure 72. Pull-Up Resistor Example ..............................................................................145
Figure 73. G3-S0 Transition ............................................................................................148
Figure 74. S0-S3-S0 Transition .......................................................................................149
Figure 75. S0-S5-S0 Transition .......................................................................................150
Figure 76. VDDQ Power Sequencing Circuit...................................................................152
Figure 77. Example 1.85V/3.3V Power Sequencing Circuit ............................................153
Figure 78. 3.3V/V5REF Sequencing Circuitry .................................................................154
Figure 79. V5REF Circuitry..............................................................................................169