Intel 815 - Manual (Page 8)

R
8 Intel
®
815 Chipset Platform Design Guide
Figures
Figure 1. System Block Diagram .......................................................................................17
Figure 2. GMCH Block Diagram ........................................................................................18
Figure 3. Board Construction Example for 60 Ω Nominal Stackup ...................................25
Figure 4. GMCH 544-Ball µ BGA* CSP Quadrant Layout (Top View)................................27
Figure 5. ICH 241-Ball µ BGA* CSP Quadrant Layout (Top View).....................................28
Figure 6. Firmware Hub (FWH) Packages ........................................................................28
Figure 7. Future 0.13 Micron Socket 370 Processor Safeguard for Universal Socket 370
Designs Using A-2 GMCH..........................................................................................31
Figure 8. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit..................32
Figure 9. VTT Selection Switch .........................................................................................33
Figure 10. Switching Pin AG1............................................................................................34
Figure 11. Processor Identification Strap on GMCH .........................................................35
Figure 12. VTTPWRGD Configuration Circuit ...................................................................36
Figure 13. GTL_REF/VCMOS_REF Voltage Divider Network ..........................................37
Figure 14. Resistor Divider Network for Processor PWRGOOD.......................................38
Figure 15. Voltage Switch For APIC Clock from Clock Synthesizer to Processor.............39
Figure 16. GTLREF Circuit Topology ................................................................................40
Figure 17. Gating Power to Intel ® CK-815 .........................................................................41
Figure 18. PWROK Gating Circuit For ICH .......................................................................42
Figure 19. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)..46
Figure 20. AGTL/AGTL+ Trace Routing............................................................................47
Figure 21. Routing for THRMDP and THRMDN................................................................50
Figure 22. Example Implementation of THERMTRIP Circuit ............................................51
Figure 23. BSEL[1:0] Circuit Implementation for PGA370 Designs...................................56
Figure 24. Examples for CLKREF Divider Circuit..............................................................57
Figure 25. RESET#/RESET2# Routing Guidelines ...........................................................58
Figure 26. Filter Specification ............................................................................................60
Figure 27. Example PLL Filter Using a Discrete Resistor .................................................62
Figure 28. Example PLL Filter Using a Buried Resistor ....................................................62
Figure 29. Core Reference Model .....................................................................................63
Figure 30. Capacitor Placement on the Motherboard........................................................64
Figure 31. Heatsink Volumetric Keepout Regions.............................................................66
Figure 32. Motherboard Component Keepout Regions.....................................................66
Figure 33. TAP Connector Comparison ............................................................................67
Figure 34. System Memory Routing Guidelines ................................................................69
Figure 35. System Memory Connectivity (2 DIMM) ...........................................................70
Figure 36. System Memory 2-DIMM Routing Topologies..................................................71
Figure 37. System Memory Routing Example ...................................................................72
Figure 38. System Memory Connectivity (3 DIMM) ...........................................................73
Figure 39. System Memory 3-DIMM Routing Topologies..................................................74
Figure 40. Intel ® 815 Chipset Platform Decoupling Example ............................................76
Figure 41. Intel ® 815 Chipset Platform Decoupling Example ............................................77
Figure 42. AGP Left-Handed Retention Mechanism .........................................................81
Figure 43. AGP Left-Handed Retention Mechanism Keepout Information........................81
Figure 44. AGP 2X/4X Routing Example for Interfaces < 6 Inches and GPA/AGP
Solutions.....................................................................................................................85
Figure 45. AGP Decoupling Capacitor Placement Example .............................................89
Figure 46. AGP VDDQ Generation Example Circuit .........................................................94
Figure 47. AGP 2.0 VREF Generation and Distribution.....................................................96
Figure 48. Display Cache Input Clocking.........................................................................100