Intel 815 - Manual (Page 4)

R
4 Intel
®
815 Chipset Platform Design Guide
5.2 General Topology and Layout Guidelines.............................................................46
5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals ...........................47
5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS)
Signals .................................................................................49
5.2.1.2 THRMDP and THRMDN ......................................................50
5.2.1.3 Additional Routing and Placement Considerations..............50
5.3 Electrical Differences for Universal PGA370 Designs ..........................................51
5.3.1 THERMTRIP Circuit ..............................................................................51
5.3.1.1 THERMTRIP Timing ............................................................51
5.4 PGA370 Socket Definition Details ........................................................................52
5.5 BSEL[1:0] Implementation Differences.................................................................56
5.6 CLKREF Circuit Implementation...........................................................................57
5.7 Undershoot/Overshoot Requirements ..................................................................57
5.8 Processor Reset Requirements............................................................................58
5.9 Processor PLL Filter Recommendations ..............................................................59
5.9.1 Topology................................................................................................59
5.9.2 Filter Specification .................................................................................59
5.9.3 Recommendation for Intel Platforms.....................................................61
5.9.4 Custom Solutions ..................................................................................63
5.10 Voltage Regulation Guidelines..............................................................................63
5.11 Decoupling Guidelines for Universal PGA370 Designs ........................................63
5.11.1 VCC
CORE
Decoupling Design.................................................................63
5.11.2 VTT Decoupling Design ........................................................................64
5.11.3 VREF Decoupling Design......................................................................64
5.12 Thermal Considerations........................................................................................65
5.12.1 Heatsink Volumetric Keepout Regions..................................................65
5.13 Debug Port Changes ............................................................................................67
6 System Memory Design Guidelines...................................................................................69
6.1 System Memory Routing Guidelines.....................................................................69
6.2 System Memory 2-DIMM Design Guidelines ........................................................70
6.2.1 System Memory 2-DIMM Connectivity ..................................................70
6.2.2 System Memory 2-DIMM Layout Guidelines .........................................71
6.3 System Memory 3-DIMM Design Guidelines ........................................................73
6.3.1 System Memory 3-DIMM Connectivity ..................................................73
6.3.2 System Memory 3-DIMM Layout Guidelines .........................................74
6.4 System Memory Decoupling Guidelines ...............................................................75
6.5 Compensation.......................................................................................................77
7 AGP/Display Cache Design Guidelines.............................................................................79
7.1 AGP Interface .......................................................................................................79
7.1.1 Graphics Performance Accelerator (GPA) ............................................80
7.1.2 AGP Universal Retention Mechanism (RM) ..........................................80
7.2 AGP 2.0 ................................................................................................................82
7.2.1 AGP Interface Signal Groups ................................................................83
7.3 Standard AGP Routing Guidelines .......................................................................84
7.3.1 1X Timing Domain Routing Guidelines .................................................84
7.3.1.1 Flexible Motherboard Guidelines .........................................84
7.3.1.2 AGP-Only Motherboard Guidelines......................................84
7.3.2 2X/4X Timing Domain Routing Guidelines............................................84
7.3.2.1 Flexible Motherboard Guidelines .........................................85