Intel 815 - Manual (Page 18)

Introduction
R
18 Intel
®
815 Chipset Platform Design Guide
1.3.2 Component Features
Figure 2. GMCH Block Diagram
System bus (66/100/133 MHz)
Processor I/F
System
memory I/F
AGP I/F
Local memory I/F
Hub I/F
Data
stream
control &
dispatch
Primary display
Overlay
H/W cursor
3D pipeline
2D (blit engine)
RAMDAC
FP / TVout
Internal graphics
GPA
or AGP
2X/4X
card
Hub
SDRAM
100/133
MHz, 64 bit
Monitor
Digital
video out
comp_blk_1
1.3.2.1 Graphics Memory Controller Hub (GMCH)
•
Processor/System Bus Support

Optimized for Intel
®
Pentium
®
III processors (CPUID = 068xh) at 133 MHz system bus
frequency

Support for Intel ® Celeron™ processors (CPUID = 068xh); 66 MHz system bus

Supports 32-bit AGTL or AGTL+ bus addressing

Supports uniprocessor systems

Utilizes AGTL and AGTL+ bus driver technology (gated AGTL/AGTL+ receivers for
reduced power)
•
Integrated DRAM controller

32 MB to 512 MB using 16-Mb/64-Mb/128-Mb technology

Supports up to three double-sided DIMMS (six rows)

100 MHz, 133 MHz SDRAM interface

64-bit data interface

Standard Synchronous DRAM (SDRAM) support (x-1-1-1 access)

Supports only 3.3V DIMM DRAM configurations

No registered DIMM support

Support for symmetrical and asymmetrical DRAM addressing

Support for x8, x16 DRAM device width

Refresh mechanism: CAS-before-RAS only

Support for DIMM serial PD (presence detect) scheme via SMbus interface

STR power management support via self-refresh mode using CKE