Intel 815 - Manual (Page 150)

Power Delivery
R
150 Intel
®
815 Chipset Platform Design Guide
Figure 75. S0-S5-S0 Transition
DRAM active DRAM in STR (CKE low) DRAM active
Clocks valid Clocks invalid Clocks valid
t16 t15
t9
t22
t8
t26
t25
t23 t21
t17
t13
t12
t11 t20
t19
t7 t18
t24
Vcc3.3sus
RSMRST#
STPCLK#
Stop grant cycle
CPUSLP#
Go_C3 from ICH
Ack_C3 from GMCH
DRAM
SUS_STAT#
PCIRST#
Cycle 1 from GMCH
Cycle 1 from ICH
Cycle 2 from GMCH
Cycle 2 from ICH
CPURST#
SLP_S3#
SLP_S5#
PWROK
Vcc3.3core
Clocks
Freq straps
Wake event
pwr_S0-S5-S0_trans