Intel 815 - Manual (Page 6)

R
6 Intel
®
815 Chipset Platform Design Guide
10.2.5 Layout for Both Host-Side and Device-Side Cable Detection .............118
10.3 AC’97 ..................................................................................................................119
10.3.1 AC’97 Routing .....................................................................................119
10.3.2 AC’97 Signal Quality Requirements ....................................................121
10.3.3 Motherboard Implementation ..............................................................121
10.4 Using Native USB Interface ................................................................................122
10.5 I/O APIC (I/O Advanced Programmable Interrupt Controller).............................123
10.6 SMBus ................................................................................................................124
10.7 PCI ......................................................................................................................124
10.8 LPC/FWH............................................................................................................125
10.8.1 In-Circuit FWH Programming..............................................................125
10.8.2 FWH V
PP
Design Guidelines ...............................................................125
10.9 RTC.....................................................................................................................125
10.9.1 RTC Crystal.........................................................................................126
10.9.2 External Capacitors .............................................................................126
10.9.3 RTC Layout Considerations ................................................................127
10.9.4 RTC External Battery Connection .......................................................127
10.9.5 RTC External RTCRESET Circuit .......................................................128
10.9.6 RTC-Well Input Strap Requirements...................................................128
10.9.7 RTC Routing Guidelines......................................................................129
10.9.8 Guidelines to Minimize ESD Events ....................................................129
10.9.9 VBIAS and DC Voltage and Noise Measurements .............................129
11 Clocking...........................................................................................................................131
11.1 2-DIMM Clocking ................................................................................................131
11.2 3-DIMM Clocking ................................................................................................133
11.3 Clock Routing Guidelines....................................................................................135
11.4 Clock Decoupling ................................................................................................137
11.5 Clock Driver Frequency Strapping ......................................................................137
11.6 Clock Skew Assumptions ...................................................................................138
11.7 Intel ® CK-815 Power Gating On Wake Events ...................................................139
12 Power Delivery.................................................................................................................141
12.1 Thermal Design Power .......................................................................................144
12.1.1 Pull-Up and Pull-Down Resistor Values ..............................................144
12.2 ATX Power Supply PWRGOOD Requirements..................................................145
12.3 Power Management Signals ...............................................................................146
12.3.1 Power Button Implementation .............................................................147
12.4 1.85V/3.3V Power Sequencing ...........................................................................148
12.4.1 VDDQ/VCC1_85 Power Sequencing ..................................................152
12.4.2 1.85V/3.3V Power Sequencing............................................................152
12.4.3 3.3V/V5REF Sequencing.....................................................................154
13 System Design Checklist.................................................................................................155
13.1 Design Review Checklist ....................................................................................155
13.2 Processor Checklist ............................................................................................155
13.2.1 GTL Checklist......................................................................................155
13.2.2 CMOS Checklist ..................................................................................156
13.2.3 TAP Checklist for 370-Pin Socket Processors ....................................156
13.2.4 Miscellaneous Checklist for 370-Pin Socket Processors ....................156
13.3 GMCH Checklist .................................................................................................158