Agp/display cache design guidelines, Agp interface, 7agp/display cache design guidelines – Intel 815 User Manual
Page 79: 1 agp interface
AGP/Display Cache Design Guidelines
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Intel
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815 Chipset Platform Design Guide
79
7
AGP/Display Cache Design
Guidelines
For the detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms) refer to
the latest AGP Interface Specification, Revision 2.0, which can be obtained from
his design guide focuses only on specific Intel 815 chipset platform
recommendations and covers both standard add-in card AGP and down AGP solutions.
7.1 AGP
Interface
A single AGP connector is supported by the GMCH’s AGP interface. LOCK# and SERR#/PERR#
are not supported. See the display cache discussion for a display cache/AGP muxing description
and a description of the Graphics Performance Accelerator (GPA).
The AGP buffers operate in one of two selectable modes to support the AGP universal connector:
•
3.3V drive, not 5V safe. This mode is compliant with the AGP 1.0 66 MHz specification.
•
1.5V drive, not 3.3V safe. This mode is compliant with the AGP 2.0 specification.
The AGP 4X must operate at 1.5V and only use differential clocking mode. The AGP 2X can
operate at 3.3V or 1.5V. The AGP interface supports up to 4X AGP signaling, though 4X fast
writes are not supported. AGP semantic cycles to DRAM are not snooped on the host bus.
The GMCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously.
Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. The
GMCH contains a 32-deep AGP request queue. High-priority accesses are supported. All AGP
semantic accesses hitting the graphics aperture pass through an address translation mechanism
with a fully-associative 20-entry TLB.
Accesses between AGP and the hub interface are limited to hub interface-originated memory
writes to AGP. Cacheable accesses from the IOQ queue flow through one path, while aperture
accesses follow another path. Cacheable AGP (SBA, PIPE#, and FRAME#) reads to DRAM all
snoop the cacheable global write buffer (GWB) for system data coherency. Aperture AGP (SBA,
PIPE#) reads to DRAM snoop the aperture queue (GCMCRWQ). Aperture AGP (FRAME#) reads
and writes to DRAM proceed through a FIFO and there is no RAW capability, so no snoop is
required.
The AGP interface is clocked from the 66 MHz clock (3V66). The AGP-to-host/memory interface
is synchronous with a clock ratio of 1:1 (66 MHz : 66 MHz), 2:3 (66 MHz : 100 MHz) and
1:2 (66 MHz : 133 MHz).