Intel 815 - Manual (Page 132)

Clocking
R
132 Intel
®
815 Chipset Platform Design Guide
Figure 68. Platform Clock Architecture (2 DIMMs)
GMCH
CPU 2_ITP
APIC 0
CPU 1
CPU 0
2.5 V
Clock Synthesizer
PW RDW N#
SEL1
SEL0
SData
SClk
SDRAM(0)
SDRAM(1)
SDRAM(2)
SDRAM(3)
SDRAM(4)
SDRAM(5)
SDRAM(6)
SDRAM(7)
DCLK
3V66 0
DOT
3V66 1
REF
PCI 0 / ICH
USB
3.3 V
APIC 1
2.5 V
PCI 1
PCI 2
PCI 3
PCI 4
PCI 5
PCI 6
PCI 7
3.3 V
52
55
50
49
32
29
28
30
31
46
45
43
42
40
39
37
36
34
7
26
8
1
11
25
54
12
13
15
16
18
19
20
Main
Mem ory
2 DIMMs
AGP
Data
Address
Control
Host unit
Graphics
Mem ory
unit
Hub I/F
Dot clock
ITP Processor
I/O Controller Hub 32.768 kHz
SIO
PCI total of 6
devices (µATX)
5 slots + 1 down
clk_arch_2DIMM
14.318 MHz