Maxim Integrated DS21Q55 - Manual (Page 8)

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TABLE OF CONTENTS
1.1 FEATURE HIGHLIGHTS ............................................................................................................................4
1.1.1 General .................................................................................................................................................. 4
1.1.2 Line Interface....................................................................................................................................... 4
1.1.3 Clock Synthesizer .............................................................................................................................. 4
1.1.4 Jitter Attenuator................................................................................................................................... 4
1.1.5 Framer/Formatter............................................................................................................................... 5
1.1.6 System Interface................................................................................................................................. 5
1.1.7 HDLC Controllers ............................................................................................................................... 6
1.1.8 Test and Diagnostics ........................................................................................................................ 6
1.1.9 Extended System Information Bus ............................................................................................... 6
1.1.10 Control Port .......................................................................................................................................... 6
1.2 DOCUMENT REVISION HISTORY .......................................................................................................12
2. BLOCK DIAGRAM ...........................................................................................................................................13
3. PIN FUNCTION DESCRIPTION ..................................................................................................................14
3.1 T RANSMIT S IDE P INS .....................................................................................................................................14
3.2 R ECEIVE S IDE P INS ........................................................................................................................................16
3.3 P ARALLEL C ONTROL P ORT P INS .................................................................................................................18
3.4 E XTENDED S YSTEM I NFORMATION B US .....................................................................................................20
3.5 JTAG T EST A CCESS P ORT P INS ...................................................................................................................20
3.6 L INE I NTERFACE P INS ....................................................................................................................................21
3.7 S UPPLY P INS ...................................................................................................................................................22
3.8 P INOUT ............................................................................................................................................................23
3.9 P ACKAGE .........................................................................................................................................................29
4. PARALLEL PORT ............................................................................................................................................30
4.1 R EGISTER M AP ...............................................................................................................................................30
5. SPECIAL PER-CHANNEL REGISTER OPERATION .........................................................................36
6. PROGRAMMING MODEL ..............................................................................................................................38
6.1 P OWER -U P S EQUENCE ..................................................................................................................................39
6.1.1 Master Mode Register ....................................................................................................................39
6.2 I NTERRUPT H ANDLING ..................................................................................................................................40
6.3 S TATUS R EGIST ERS ........................................................................................................................................40
6.4 I NFORMATION R EGISTERS ............................................................................................................................41
6.5 I NTERRUPT I NFORMATION R EGISTERS ........................................................................................................41
7. CLOCK MAP .......................................................................................................................................................42
8. T1 FRAMER/FORMATTER CONTROL REGISTERS .........................................................................43
8.1 T1 C ONTROL R EGISTERS ..............................................................................................................................43
8.2 T1 T RANSMIT T RANSPARENCY ....................................................................................................................48
8.3 T1 R ECEIVE -S IDE D IGITAL -M ILLIWATT C ODE G ENERATION .................................................................48
8.4 T1 I NFORMATION R EGISTER ........................................................................................................................50
9. E1 FRAMER/FORMATTER CONTROL REGISTERS .........................................................................52
9.1 E1 C ONTROL R EGISTERS ..............................................................................................................................52
9.2 A UTOMATIC A LARM G ENERATION .............................................................................................................56
9.3 E1 I NFORMATION R EGISTERS .......................................................................................................................57
10. COMMON CONTROL AND STATUS REGISTERS .........................................................................59
11. I/O PIN CONFIGURATION OPTIONS ...................................................................................................66