Maxim Integrated DS21Q55 User Manual
Page 216
Product Preview
DS21Q55
216 of 248
012103
Please contact
or search
http://www.maxim-ic.com
for updated
information.
TRANSMIT SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled)
Figure 35-9
NOTE:
1) TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG
will be ignored during channel 24).
LSB
F
MSB
LSB MSB
CHANNEL 1
CHANNEL 24
A
B
C/A
D/B
A
B
C/A D/B
TSYSCLK
TSER
TSSYNC
TSIG
TCHCLK
TCHBLK
CHANNEL 23
A
CHANNEL 23
CHANNEL 24
CHANNEL 1
1