Maxim Integrated DS21Q55 User Manual

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TRANSMIT SIDE BOUNDARY TIMING, TSYSCLK = 1.544MHz (With Elastic
Store Enabled) Figure 35-20

NOTES:

1) The F-bit position in the TSER data is ignored.
2) TCHBLK is programmed to block channel 24.

LSB

MSB

LSB MSB

CHANNEL 1

CHANNEL 24

TSYSCLK

TSER

TSSYNC

TCHCLK

TCHBLK

CHANNEL 23