BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 85)

Ethernet Interface
Slave Controller – IP Core for Xilinx FPGAs III-73
9.3 RMII Interface
The IP Core supports RMII with 2 communication ports. Nevertheless, MII is recommended since the
PHY delay (and delay jitter) is smaller in comparison to RMII.
The Beckhoff ESCs have additional requirements to Ethernet PHYs using RMII, which are easily
accomplished by several PHY vendors.
Refer to “Section I – Technology” for Ethernet PHY requirements.
Additional information regarding the IP Core:

The clock source of the PHYs is the same as for the FPGA (25 MHz quartz oscillator)

The signal polarity of nRMII_LINK is not configurable inside the IP Core, nRMII_LINK is active low.
If necessary, the signal polarity must be swapped outside the IP Core.

The IP Core can be configured to use the MII management interface for link detection and link
configuration.

The IP Core supports an arbitrary PHY address offset.
For details about the ESC RMII Interface refer to Section I.
9.3.1 RMII Interface Signals
The RMII interface of the IP Core has the following signals:
EtherCAT
device
nRMII_LINK
CLK50
RMII_RX_DV
RMII_RX_ERR
RMII_RX_DATA[1:0]
RMII_TX_ENA
RMII_TX_DATA[1:0]
Figure 32: RMII Interface signals
Table 38: RMII Interface signals
Signal Direction Description
CLK50 IN RMII RX/TX reference clock (50 MHz)
nRMII_LINK IN Input signal provided by the PHY if a 100 Mbit/s (Full
Duplex) link is established (alias LINK_MII)
RMII_RX_DV IN Carrier sense/receive data valid
RMII_RX_DATA[1:0] IN Receive data (alias RXD)
RMII_RX_ERR IN Receive error (alias RX_ER)
RMII_TX_ENA OUT Transmit enable (alias TX_EN)
RMII_TX_DATA[1:0] OUT Transmit data (alias TXD)