4 mii example schematic, Mii example schematic, Figure 31: mii example schematic – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual

Page 84: Ethercat ip core ethernet phy, Dcm/pll, 25 mhz, Optional

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Ethernet Interface

III-72

Slave Controller

– IP Core for Xilinx FPGAs

9.2.4

MII example schematic

Refer to chapter 8.4 for more information on special markings (!).Take care of proper compensation of
the TX_CLK phase shift.

EtherCAT IP Core

Ethernet PHY

MII_RX_DV

MII_RX_DATA[3:0]

MII_RX_ERR

MII_TX_ENA

MII_TX_DATA[3:0]

MII_RX_CLK

RX_DV

RXD[3:0]

RX_ER

TX_EN

TXD[3:0]

RX_CLK

CLK25

CRS

TX_ER

COL

nMII_LINK

LINK_STATUS

CLK25

DCM/PLL

CLK_IN

CLK25

CLK100

25 MHz

MDIO

MCLK

MDIO

MDC

CC I/O

TX_CLK

! optional

MII_TX_CLK

! optional

MII_TX_SHIFT[1:0]

00/01/10/11

Figure 31: MII example schematic

This manual is related to the following products:

EtherCAT IP Core for Altera FPGAs v2.4.4