BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 57)

Example Designs
Slave Controller – IP Core for Xilinx FPGAs III-45
6 Example Designs
Example designs are available for:

Avnet Xilinx Spartan-6 LX150T Development Kit with MII and Digital I/O PDI

Avnet Xilinx Spartan-6 LX150T Development Kit with MII, PLB-to-AXI bridge, and Microblaze
processor
The EtherCAT master uses an XML file which describes the device and its features. The XML device
description file for all example designs and its schema can be found in the installation directory.
\example_designs\EtherCAT_Device_Description\
Projects have to be compiled and then can be loaded to the SPI configuration devices of the
evaluation board.
The EtherCAT IP core example design resource consumption figures for the PLB design are based on
EtherCAT IP Core for Xilinx FPGAs Version 2.04a and Xilinx ISE 12.4.
The EtherCAT IP core example design resource consumption figures for the Digital I/O design are
based on EtherCAT IP Core for Xilinx FPGAs Version 2.04e and Xilinx EDK 14.7.