BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 66)

IP Core Signals
III-54 Slave Controller – IP Core for Xilinx FPGAs
CLK25
EtherCAT IP Core Ethernet
PHY
RMII
REF_CLK
DCM/PLL
CLK_IN CLK25
CLK100 CLK100
Ethernet
PHY
RMII
REF_CLK
50 MHz
CLK50 CLK50
FPGA
Figure 25: EtherCAT IP Core clock source (RMII)
8.2 SII EEPROM Interface Signals
Table 19: SII EEPROM Signals
Condition Name Direction Description
PROM_SIZE INPUT
Sets EEPROM size:
0: up to 16 kbit EEPROM
1: 32 kbit-4Mbit EEPROM
Tristate drivers inside
core (EEPROM/MI)
PROM_CLK OUTPUT
EEPROM I²C Clock
(output values: 0 or Z)
External tristate drivers
for EEPROM/MI
PROM_CLK OUTPUT
EEPROM I²C Clock
(output values: 0 or 1)
Tristate drivers inside
core (EEPROM/MI)
PROM_DATA BIDIR EEPROM I²C Data
External tristate drivers
for EEPROM/MI
PROM_DATA_IN INPUT
EEPROM I²C Data:
EEPROM  IP Core
PROM_DATA_OUT OUTPUT
EEPROM I²C Data:
IP Core  EEPROM
(always 0)
PROM_DATA_ENA OUTPUT
0: disable output driver for
PROM_DATA_OUT
1: enable output driver for
PROM_DATA_OUT