BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 4)

CONTENTS
III-IV Slave Controller – IP Core for Xilinx FPGAs
CONTENTS
1 Overview 1
1.1 Frame processing order 2
1.2 Scope of this document 3
1.3 Scope of Delivery 3
1.4 Target FPGAs 4
1.5 Designflow requirements 4
1.6 Tested FPGA/Designflow combinations 5
1.7 Release Notes 6
1.8 Design flow 8
1.9 IP Core Evaluation 9
1.10 Simulation 10
2 Features and Registers 11
2.1 Features 11
2.2 Registers 15
2.3 Extended ESC Features in User RAM 19
3 IP Core Installation 21
3.1 Installation on Windows PCs 21
3.1.1 System Requirements 21
3.1.2 Installation 21
3.2 Installation on Linux PCs 22
3.2.1 System Requirements 22
3.2.2 Installation 22
3.3 Files located in the lib folder 22
3.4 License File 23
3.5 IP Core Vendor ID Package 23
3.6 RSA Decryption Keys 24
3.7 Environment Variable 24
3.8 Integrating the EtherCAT IP Core into the Xilinx Designflow 25
3.9 Software Templates for example designs with Microblaze processor (EDK) 25
3.10 EtherCAT Slave Information (ESI) / XML device description for example designs 25
4 IP Core Usage 26
4.1 IPCore_Config Tool 26
4.2 EDK designs with EtherCAT IP Core 27
4.3 Vivado designs with EtherCAT IP Core 31
5 IP Core Configuration 32
5.1.1 Product ID tab 33
5.1.2 Physical Layer tab 34
5.1.3 Internal Functions tab 35
5.1.4 Feature Details tab 36