BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 62)

FPGA Resource Consumption
III-50 Slave Controller – IP Core for Xilinx FPGAs
7 FPGA Resource Consumption
The resource consumption figures shown in this chapter reflect results of example synthesis runs and
can only be used for rough resource estimations. The figures are subject to quite large variations
depending on design tools and version, FPGA type, constraints (e.g., area vs. speed), total FPGA
utilization (design tools typically stop optimization if the timing goal is reached), etc. No extra effort
was undertaken to achieve optimum results, i.e. by sophisticated constraining and design flow setting.
For accurate resource consumption figures, please use the evaluation license of the EtherCAT IP
Core and synthesize your individual configuration for the desired FPGA.
The figures of the following table do not imply that the individual features are operational in the
selected FPGA (i.e., that the resources are sufficient or that timing closure is achievable). The
synthesis runs where performed without timing constraints, without location constraints, and without
bitstream generation.
The EtherCAT IP core resource consumption overview figures are based on EtherCAT IP Core for
Xilinx FPGAs Version 2.03a, Xilinx ISE 11.4, and Xilinx Spartan-3E or Spartan-6 devices. One
Spartan-3E slice contains 2 lookup-tables (LUT4) and 2 flip-flops, a Spartan-6 slice contains 4 lookup-
tables (LUT6) and 4 flip-flops. The number of slices is shown for very rough estimations, because they
highly depend on the optimization process. Registers and logic can be combined in slices or
implemented separately, depending on the device utilization and placement, so the variation of the
slices figure is extremely high. The registers and logic LUT figures are more stable, but also subject to
variation as a result of optimization.