BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 46)

IP Core Configuration
III-34 Slave Controller – IP Core for Xilinx FPGAs
5.1.2 Physical Layer tab
Figure 14: Physical Layer tab
Communication Ports
The number of communication ports by default is two. As PHY interface MII (1, 2, or 3 ports) or RMII
(1 or 2 ports only) can be selected. It is recommended to use MII as for accuracy of the distributed
clocks is much better with MII.
PHY Management Interface
The PHY Management Interface function can be selected or deselected. If it deselected, the other MII
Configuration options are not available.
TX Shift
Automatic or manual TX Shift is available if TX Shift is selected. TX Shift delays MII TX signals to
comply to Ethernet PHY setup and hold timing. Automatic TX Shift uses the TX_CLK signals of the
PHYs to detect appropriate TX Shift settings automatically. Manual TX Shift configuration allows for
delaying the MII TX signals by 0, 10, 20, or 30 ns.
LINK state and PHY configuration through MI
MI link detection and configuration is available if checked. Ethernet PHYs are configured and link
status is polled via the MII Management Interface. Enhanced link detection has to be activated if MI
link detection and configuration is used and the nMII_LINK0/1/2 signals are not used.
Enhanced link detection
Enhanced MII link detection is a mechanism of informing link partners of receive errors.
Tristate Driver inside core (EEPROM/MI)
If selected tri-state drivers of the core are used for access to EEPROM and PHY Management signals.
This function should not be enabled when the OPB/PLB Process Data Interface is used. This is also
marked in the output window at the bottom.