BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 7)

CONTENTS
Slave Controller – IP Core for Xilinx FPGAs III-VII
10.5.1 Interface 104
10.5.2 Configuration 105
10.5.3 Byte Enable (BE) 105
10.5.4 Timing specifications 106
11 Distributed Clocks SYNC/LATCH Signals 108
11.1 Signals 108
11.2 Timing specifications 108
12 SII EEPROM Interface (I²C) 109
12.1 Signals 109
12.2 EEPROM Emulation 109
12.3 Timing specifications 109
13 Electrical Specifications 110
14 Synthesis Constraints 111
15 Appendix 114
15.1 Support and Service 114
15.1.1 Beckhoff’s branch offices and representatives 114
15.2 Beckhoff Headquarters 114