BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 18)

Overview
III-6 Slave Controller – IP Core for Xilinx FPGAs
1.7 Release Notes
EtherCAT IP Core updates deliver feature enhancements and removed restrictions. Feature
enhancements are not mandatory regarding conformance to the EtherCAT standard. Restrictions
have to be judged whether they are relevant i
n the user’s configuration or not, or if workarounds are
possible.
Table 4: Release notes
Version Release notes
2.04a
(03/2011) 
Update to ISE 12.4/13.1

Station Alias register (0x0012:0x0013) is now permanently enabled

Extended DL Control register (0x0102:0x0103) is now permanently enabled

ECAT Event Mask register (0x0200:0x0201) is now permanently enabled

AL Control register (0x0120:0x0121) and AL Status register (0x0130:0x0131) are
now 16 bit wide
Enhancements:

Added example design for Avnet/Xilinx Spartan-6 LX150T Development Kit
Restrictions of this version, which are removed in V2.04d:

Reduced receive time accuracy when Receive Times are enabled while Distributed
Clocks are disabled.
Restrictions of this version, which are removed in V2.04e:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60
Kbyte RAM configuration.
2.04d
(07/2013) 
Update to ISE 14.5
Enhancements:

PlanAhead and Vivado support added

Xilinx Artix-7, Zynq-7000 support added

RX FIFO size initialized by SII EEPROM

MI link detection: relaxed checking of PHY register 9 (1000Base-T Master-Slave
Control register)
Restrictions of previous versions which are removed in this version:

Improved receive time accuracy when Receive Times are enabled while Distributed
Clocks are disabled (customers using this configuration in V2.04a should update to
V2.04d)
Restrictions of this version, which are removed in V2.04e:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60
Kbyte RAM configuration.
2.04e
(01/2015) 
Update to ISE 14.7

The EL9800/FB1130 example designs have been removed because these
evaluation boards are no longer available.
Enhancements

Xilinx Kintex UltraScale, Virtex UltraScale are now supported

Added LX150T DIGI example design

For EEPROM Emulation, the CRC error bit 0x0502[11] can be written via PDI to
indicate CRC errors during a reload command.

The ESI XML device description does not use special data types anymore.

Internal license attribute encoding updated (issues with Vivado 2012.x)

The LX150T PLB example design now supports the PHY management interface
correctly
Restrictions of previous versions which are removed in this version:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) can be used in the 60 Kbyte
RAM configuration.