BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 125)

Synthesis Constraints
Slave Controller – IP Core for Xilinx FPGAs III-113
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### MII Port 2 ###
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### Receive clock period 40 ns/25 MHz ###
TIMESPEC TS_RX_CLK2 = PERIOD TM_RX_CLK2 40000 ps;
Net MII_RX_CLK2 TNM_NET = TM_RX_CLK2;
### RX_DV/RX_DATA setup 10 ns, hold 10 ns ###
OFFSET = IN 10 ns VALID 20 ns BEFORE MII_RX_CLK2;
### TX_ENA/TX_DATA maximum clock-to-pad 10 ns ###
### (manually check minimum clock-to-pad = 0 ns) ###
### TX_CLK from PHY to REF_CLK phase shift has to be ###
### determined and compensated using TX-Shift or registers ###
TIMEGRP TM_TX2 OFFSET = OUT 10 ns AFTER REF_CLK;
Net MII_TX_ENA2 TNM_NET=TM_TX2;
Net MII_TX_DATA2<0> TNM_NET=TM_TX2;
Net MII_TX_DATA2<1> TNM_NET=TM_TX2;
Net MII_TX_DATA2<2> TNM_NET=TM_TX2;
Net MII_TX_DATA2<3> TNM_NET=TM_TX2;
Net MII_TX_ERR2 TNM_NET=TM_TX2;