BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 36)

IP Core Installation
III-24 Slave Controller – IP Core for Xilinx FPGAs
3.6 RSA Decryption Keys
The Xilinx XST synthesis flow requires two decryption keys for decrypting the EtherCAT IP Core
during synthesis. These two keys can be found in the <IPInst_dir>\lib folder of the IP core installation:

rsa_ethercat_base_pvt.pem

rsa_ethercat_ip__eval_pvt.pem (Evaluation of the EtherCAT IP Core)
or
rsa_ethercat_ip__full_pvt.pem
(Full version of the EtherCAT IP Core)
These keys have to be copied to the application folder of your user profile:
%APPDATA%\RSA\ 2 (Windows)
or
$HOME/.rsa/ (Linux)
or they can be copied into the design tool installation folders (available to all users):
ISE_DS\ISE\data (ISE)
ISE_DS\PlanAhead\tps\isl (PlanAhead)
Vivado\\tps\isl (Vivado)
On Windows, all this is automatically performed during IP Core installation (except for Vivado).
3.7 Environment Variable
If you use the EDK, the following environment variable should be set:
ETHERCAT_XIL_INST = <IPInst_dir>
Example:
ETHERCAT_XIL_INST = C:\BECKHOFF\ethercat-
This allows the configuration tool to locate all necessary files for completing a user configured IP Core.
You can select to set the environment variable by EtherCAT IP Core Setup program (Windows PCs
only).
2 E.g., C:\users\\AppData\Roaming\RSA (Windows 7 english) or
C:\Benutzer\\AppData\Roaming\RSA (Windows 7 german) or
C:\Documents and Settings\\Application Data\RSA (Windows XP english) or
C:\Dokumente und Einstellungen\\Anwendungsdaten\RSA (Windows XP german)