BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 12)

ABBREVIATIONS
III-XII Slave Controller – IP Core for Xilinx FPGAs
ABBREVIATIONS
µC
Microcontroller
ADR Address
AL Application Layer
BHE Bus High Enable
BSP Board Support Package
CMD Command
CS Chip Select
DC Distributed Clock
DCM Digital Clock Manager
DL Data Link Layer
ECAT EtherCAT
EDK Embedded Development Kit (Xilinx software)
EOF End of Frame
ESC EtherCAT Slave Controller
ESI EtherCAT Slave Information
FMMU Fieldbus Memory Management Unit
FPGA Field Programmable Gate Array
GPI General Purpose Input
GPO General Purpose Output
HDL Hardware Description Language
IP Intellectual Property
IRQ Interrupt Request
ISE Integrated Software Environment (Xilinx software)
LE Logic Element
LC Logic Cell
MAC Media Access Controller
MDIO Management Data Input / Output
MHS Microprocessor Hardware Specification
MI (PHY) Management Interface
MII Media Independent Interface
MISO Master In – Slave Out
MOSI Master Out – Slave In
MPD Microprocessor Peripheral Specification
OPB On-Chip Peripheral Bus
PAO Peripheral Analyze Order
PDI Process Data Interface
PLB Processor Local Bus
PLD Programmable Logic Device
PLL Phase Locked Loop
RBF Raw Binary File
RD Read
RMII Reduced Media Independent Interface
SDK Software Development Kit
SM SyncManager
SoC System on a Chip
SOF Start of Frame
SOPC System on a programmable Chip
SPI Serial Peripheral Interface
VHDL Very High Speed Integrated Circuit Hardware Description Language
WR Write