BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 61)

Example Designs
Slave Controller – IP Core for Xilinx FPGAs III-49
6.2.4 SII EEPROM
Use this ESI for the SII EEPROM:
Beckhoff Automation GmbH (Evaluation)/
IP Core example designs ET1815 (Xilinx)/
ET1815 IP Core Avnet LX150T
6.2.5 Downloadable configuration file
Two already synthesized time limited configuration files

LX150T_AXI_Demo_V2_04a_time_limited.bit
based on this digital I/O example design can be found in the
\example_designs\LX150T_PLB\
folder. After expiration of about 1 hour the design quits its operation. These files must only be used for
evaluation purposes, any distribution is not allowed.