BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 43)

IP Core Usage
Slave Controller – IP Core for Xilinx FPGAs III-31
12. Generate Bitstream:
Result is the file "system.bit" in the implementation folder of the EDK project. This configuration file
only includes the hardware parts of the design, without software for the processor.
13. Create and build a software application (Export Design – Export & Launch SDK)
14. Update Bitstream with software program information
(EDK – Device Configuration – Update Bitstream)
 Result is the file “download.bit” (= “system.bit” + “.elf”) in the
implementation folder of the EDK project.
15. Download the design into your FPGA:
a) Download temporarily into the volatile configuration memory of the FPGA via JTAG-Interface:
EDK – Device Configuration – Download Bitstream
b) Download permanently into the non-volatile configuration SPI flash via JTAG-Interface and
indirect SPI flash configuration using Xilinx IMPACT.
4.3 Vivado designs with EtherCAT IP Core
There are two basic kinds of implementing the EtherCAT IP core using Vivado:
The first option is characterized by placing the EtherCAT IP core outside of a block design. All IPs are
connected inside the block design except for the EtherCAT IP. The AXI connection for the EtherCAT
IP is an external connection of the block design. The block design is instantiated on a top-level HDL
file, which also instantiates the EtherCAT IP Core.
The second option is to use the output files of the IPCore_Config tool as input sources for an
individual IP packed with the Xilinx IP Packager. In this case, the EtherCAT IP gets another wrapper
generated by the IP Packager. The packed IP is added to the block design and connected to other IP.