BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 30)

Features and Registers
III-18 Slave Controller – IP Core for Xilinx FPGAs
Table 10: Legend
Symbol Description
x Available
- Not available
r Read only
c Configurable
dc
Available if Distributed Clocks with all
Sync/Latch signals are enabled
rt
Available if Receive Times or Distributed Clocks
are enabled (always available for 3-4 ports)
io Available if Digital I/O PDI is selected
red Register changed in this version