BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 5)

CONTENTS
Slave Controller – IP Core for Xilinx FPGAs III-V
5.1.5 Process Data Interface tab 38
6 Example Designs 45
6.1 Avnet Xilinx Spartan-6 LX150T Development Kit with Digital I/O 46
6.1.1 Configuration and resource consumption 46
6.1.2 Functionality 46
6.1.3 Implementation 47
6.1.4 SII EEPROM 47
6.2 Avnet Xilinx Spartan-6 LX150T Development Kit with PLB/AXI 48
6.2.1 Configuration and resource consumption 48
6.2.2 Functionality 48
6.2.3 Implementation 48
6.2.4 SII EEPROM 49
6.2.5 Downloadable configuration file 49
7 FPGA Resource Consumption 50
8 IP Core Signals 53
8.1 General Signals 53
8.1.1 Clock source example schematics 53
8.2 SII EEPROM Interface Signals 54
8.3 LED Signals 55
8.4 Distributed Clocks SYNC/LATCH Signals 55
8.5 Physical Layer Interface 56
8.5.1 MII Interface 57
8.5.2 RMII Interface 59
8.6 PDI Signals 60
8.6.1 General PDI Signals 60
8.6.2 Digital I/O Interface 60
8.6.3 SPI Slave Interface 61
8.6.4 Asynchronous 8/16 Bit µController Interface 61
8.6.5 PLB Processor Local Bus 63
8.6.6 OPB On-Chip Peripheral Bus 65
9 Ethernet Interface 66
9.1 PHY Management interface 66
9.1.1 PHY Management Interface Signals 66
9.1.2 PHY Address Configuration 66
9.1.3 Separate external MII management interfaces 67
9.1.4 MII management timing specifications 67
9.2 MII Interface 68
9.2.1 MII Interface Signals 69
9.2.2 TX Shift Compensation 70
9.2.3 MII Timing specifications 71
9.2.4 MII example schematic 72