BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 47)

IP Core Configuration
Slave Controller – IP Core for Xilinx FPGAs III-35
5.1.3 Internal Functions tab
Figure 15: Internal Functions tab
FMMUs
Number of FMMU instances. Between 0 and 8 FMMUs are possible.
SyncManager
Number of SyncManager instances. Between 0 and 8 SyncManagers are possible.
Process Data RAM
The size of the Process data memory can be determined in this dialog. Minimum memory size is
1 KByte, maximum memory size is 60 KByte.
Receive Times enabled
The Distributed Clocks receive time feature for propagation delay calculation can be enabled without
using all DC features. They will be automatically enabled for configurations with 3 ports.
Distributed Clocks enabled
The Distributed Clocks feature comprises synchronized distributed clocks, receive times, SyncSignal
generation, and LatchSignal time stamping.
Distributed Clocks Width
The width of the Distributed Clocks can be selected to be either 32 bit or 64 bit. DC with 64 bit require
more FPGA resources. DC with 32 bit and DC with 64 bit are interoperable.
Cyclic pulse length
Determines the length of SyncSignal output (register 0x0982:0x0983).
Mapping to global IRQ
Sync0 and Sync1 can additionally be mapped internally to the global IRQ. This might be a good
solution if a microcontroller interface is short on IRQs. However, the sync signals will remain available
on Sync0 and Sync1 outputs.