BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 6)

CONTENTS
III-VI Slave Controller – IP Core for Xilinx FPGAs
9.3 RMII Interface 73
9.3.1 RMII Interface Signals 73
9.3.2 RMII example schematic 74
10 PDI Description 75
10.1 Digital I/O Interface 76
10.1.1 Interface 76
10.1.2 Configuration 77
10.1.3 Digital Inputs 77
10.1.4 Digital Outputs 77
10.1.5 Output Enable 78
10.1.6 SyncManager Watchdog 78
10.1.7 SOF 79
10.1.8 OUTVALID 79
10.1.9 Timing specifications 79
10.2 SPI Slave Interface 81
10.2.1 Interface 81
10.2.2 Configuration 81
10.2.3 SPI access 82
10.2.4 Address modes 82
10.2.5 Commands 83
10.2.6 Interrupt request register (AL Event register) 83
10.2.7 Write access 83
10.2.8 Read access 83
10.2.9 SPI access errors and SPI status flag 84
10.2.10 2 Byte and 4 Byte SPI Masters 85
10.2.11 Timing specifications 86
10.3 Asynchronous 8/16 bit µController Interface 92
10.3.1 Interface 92
10.3.2 Configuration 92
10.3.3 µController access 93
10.3.4 Write access 93
10.3.5 Read access 93
10.3.6 µController access errors 94
10.3.7 Connection with 16 bit µControllers without byte addressing 94
10.3.8 Connection with 8 bit µControllers 95
10.3.9 Timing Specification 96
10.4 PLB Slave Interface 100
10.4.1 Interface 100
10.4.2 Configuration 101
10.4.3 Timing specifications 102
10.5 OPB Slave Interface 104