12 sii eeprom interface (i²c), 1 signals, 2 eeprom emulation – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual
Page 121: 3 timing specifications, Sii eeprom interface (i²c), Signals, Eeprom emulation, Timing specifications, Table 61: i²c eeprom signals, Table 62: eeprom timing characteristics ip core
12 sii eeprom interface (i²c), 1 signals, 2 eeprom emulation | 3 timing specifications, Sii eeprom interface (i²c), Signals, Eeprom emulation, Timing specifications, Table 61: i²c eeprom signals, Table 62: eeprom timing characteristics ip core | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual | Page 121 / 126 This manual is related to the following products: