11 distributed clocks sync/latch signals, 1 signals, 2 timing specifications – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual
Page 120: Distributed clocks sync/latch signals, Signals, Timing specifications, Table 59: distributed clocks signals, Figure 59: distributed clocks signals, Figure 60: latchsignal timing, Figure 61: syncsignal timing
11 distributed clocks sync/latch signals, 1 signals, 2 timing specifications | Distributed clocks sync/latch signals, Signals, Timing specifications, Table 59: distributed clocks signals, Figure 59: distributed clocks signals, Figure 60: latchsignal timing, Figure 61: syncsignal timing | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual | Page 120 / 126 This manual is related to the following products: