Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 78)

BIOS
iVPX7225 Installation and Use (6806800S11C) 59
5.3.1 Serial Presence Detect (SPD)
iVPX7225 Serial Presence Detect (SPD) Option ROM (Read Only Memory) is integrated into the
onboard Microchip MCP98243 Memory Module Temperature Sensors. Though the iVPX7225
is a memory-down configuration, there are two such devices onboard to provide temperature
data as well as the SPD function. One device is connected to each memory channel.
Geographically, both sensors are on the primary side of the PCB.
5.3.2 Memory Test
The BIOS will execute a short memory test after the Read and Write Training.
5.3.3 ECC Support
BIOS will always enable ECC support in the chipset.
5.3.4 DDR3 Refresh Rate
BIOS support double data rate 3 synchronous DRAM with 1600 MHz memory speed. Refresh
rate is programmed to DDR3 specifications.
5.4 Reset
The BIOS can trigger a soft or warm reset by writing the reset control register (RST_CNT) 0xCF9
with 0x04 (soft reset) or 0x06 (hard reset). Global reset can also be done by writing 0x0E.
5.5 PCIe Initialization
BIOS supports PCI Express Specification 2.1 and will enumerate all the bridges and devices
connected from the processor to PCH PCIe interface:
 Memory Controller Host-to-PCI Bridge (VID 8086, DID 0104)
 PCI-to-PCI Bridge (VID 8086, DID 0101)
 Integrated Graphics Controller (VID 8086, DID 0116)
 Universal Serial Bus (USB) Controller (VID 8086, DID 1C2D)