Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 150)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 131
7.3.1.4 Interrupt Identification Register (IIR)
In order to minimize software overhead during data character transfers, the UART prioritizes
interrupts into four levels (listed in the below table) and records these in the Interrupt
Identification Register. The Interrupt Identification Register (IIR) stores information indicating
that a prioritized interrupt is pending and the source of that interrupt.
Table 7-47 UART Interrupt Priorities2
Priority Level Interrupt Source
1 (Highest) Receiver Line Status. One or more bits were set.
2 Received Data is available. In FIFO mode, trigger level was reached; in
non-FIFO mode, RBR has data.
2 Receiver Time out occurred. It happens in FIFO mode only, when there
is data in the receive FIFO but no activity for a time period.
3 Transmitter requests data. In FIFO mode, the transmit FIFO is half or
more than half empty; in non-FIFO mode, THR is read already.
4 Modem Status: one or more of the modem input signals has changed
state.
Table 7-48 Interrupt Identification Register (IIR)
IO Address: Base +2
Bit # Description Default Access
0 Interrupt status bit:
1: no interrupt pending
0: interrupt pending 1 R
2:1 Interrupt priority level and source:
11: Receiver line status
10: Receiver data available
01: Transmitter holding register empty
00: Modem status 0 R
3 Time Out Detected:
0: No time out interrupt is pending
1: Character time-out indication (FIFO mode
only) 0 R