Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 161)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 142
When bits 0, 1, 2, or 3 are set to logic 1, a Modem Status interrupt is generated if bit 3 of the
Interrupt Enable Register is set.
Table 7-54 Modem Status Register (MSR)
IO Address: Base +6
Bit # Description Default Access
0 Change in clear-to-send (DCTS) indicator
DCTS indicates that the CTS# input has
changed state since the last time it was read
by the CPU. When DCTS is set (autoflow
control is not enabled and the modem status
interrupt is enabled), a modem status
interrupt is generated. When autoflow control
is enabled (DCTS is cleared), no interrupt is
generated:
1: Change in state of CTS# input since last read
0: No change in state of CTS# input since last
read 0 R/W
1 Change in data set ready (DDSR) indicator
DDSR indicates that the DSR# input has
changed state since the last time it was read
by the CPU. When DDSR is set and the modem
status interrupt is enabled, a modem status
interrupt is generated:
1: Change in state of DSR# input since last read
0: No change in state of DSR# input since last
read 0 R/W
2 Trailing edge of the ring indicator (TERI)
detector
TERI indicates that the RI# input to the chip
has changed from a low to a high level. When
TERI is set and the modem status interrupt is
enabled, a modem status interrupt is
generated. Not supported. 0 R/W