Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 127)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 108
7.1.12 Power Good Status 2 Register - 0x0D
7.1.13 System Status Register - 0x0E
Table 7-12 Power Good Status 2 Register - 0x0D
Bit # Description Default LPC Access I2C Access
0 5V PS Power Good Indication. Ext. RO RO
0: 5V PS power failure.
1: 5V PS power good indication.
1 2.5V PS Power Good Indication. Ext. RO RO
0: 2.5V PS power failure.
1: 2.5V PS power good indication.
7:2 Reserved 0 RO RO
Table 7-13 System Status Register - 0x0E
Bit # Description Default LPC Access I2C Access
0 CPU CATERR# Ext. RO -
0: CPU catastrophic error.
1: No CPU catastrophic error.
1 CPU THERMTRIP# Ext. RO -
0: CPU thermal trip indication.
1: No CPU thermal trip indication.
2 CPU PROCHOT# Ext. RO -
0: CPU processor hot indication.
1: No CPU processor hot indication.
3 PCH S5 Sleep Indication Ext. RO -
0: SLP_S5# sleep signal asserted.
1: SLP_S5# sleep signal de-asserted.