Artesyn iVPX7225 Installation and Use (April 2015) Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for iVPX7225 Installation and Use (April 2015) Artesyn
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 168 |
| Size: | 10.55 MB |
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Document Outline
- iVPX7225
- Contents
- About this Manual
- Safety Notes
- Sicherheitshinweise
- Introduction
- Hardware Preparation and Installation
- Controls, LEDs and Connectors
- Functional Description
- 4.1 Block Diagram
- 4.2 Processor
- 4.3 Chipset
- 4.4 System Memory
- 4.5 Ethernet Interfaces
- 4.6 PCI Express
- 4.7 SATA
- 4.8 USB
- 4.9 Serial COM
- 4.10 Video
- 4.11 GPIO
- 4.12 SMBus
- 4.13 Boot Flash
- 4.14 NAND Flash
- 4.15 FRAM
- 4.16 Trusted Platform Module
- 4.17 Real Time Clock
- 4.18 Watchdog Timer
- 4.19 XMC Support
- 4.20 Boot Firmware
- 4.21 Operating System
- BIOS
- 5.1 Overview
- 5.2 Processor Initialization
- 5.3 Memory Initialization
- 5.4 Reset
- 5.5 PCIe Initialization
- 5.6 I/O Device Configuration
- 5.7 Boot Options
- 5.8 I/O Redirection
- 5.9 BIOS Setup Layout
- 5.9.1 Main Menu
- 5.9.2 Boot Features
- 5.9.3 Advanced Menu
- 5.9.4 Processor Configuration
- 5.9.5 Processor Power Management
- 5.9.6 HDD Configuration
- 5.9.7 Memory Configuration
- 5.9.8 System Agent (SA) Configuration
- 5.9.9 Graphics Configuration
- 5.9.10 IGD Configuration
- 5.9.11 PEG Port Configuration
- 5.9.12 South Bridge Configuration
- 5.9.13 SB USB Configuration
- 5.9.14 SB Security Configuration
- 5.9.15 Network Configuration
- 5.9.16 SIO Configuration
- 5.9.17 ME Configuration
- 5.9.18 Thermal Configuration
- 5.9.19 Platform Thermal Configuration
- 5.9.20 Intel® Rapid Start Technology
- 5.9.21 iVPX7225 Menu
- 5.9.22 Security Menu
- 5.9.23 TPM Configuration
- 5.9.24 Boot Menu
- 5.9.25 Exit Menu
- 5.10 BIOS POST Codes
- 5.11 Memory POST Codes
- Maps and Registers
- FPGA Registers
- 7.1 FPGA Registers
- 7.1.1 Blade Revision Register - 0x00
- 7.1.2 FPGA Major Revision Register - 0x01
- 7.1.3 FPGA Minor Revision Register - 0x02
- 7.1.4 FPGA Date Code Register - 0x04
- 7.1.5 FPGA Month Code Register - 0x05
- 7.1.6 FPGA Year Code Register 0x06
- 7.1.7 FPGA Reset Cause Register - 0x08
- 7.1.8 Watchdog Control Register - 0x09
- 7.1.9 Watchdog Re-trigger Register - 0x0A
- 7.1.10 Memory Write Protect Register - 0x0B
- 7.1.11 Power Good Status 1 Register - 0x0C
- 7.1.12 Power Good Status 2 Register - 0x0D
- 7.1.13 System Status Register - 0x0E
- 7.1.14 Misc 1 Control and Status Register - 0x10
- 7.1.15 Misc 2 Control and Status Register - 0x11
- 7.1.16 DIP Switch Status Register - 0x14
- 7.1.17 Misc 3 Control and Status Register - 0x15
- 7.1.18 Boot Control and Status 1 Register - 0x16
- 7.1.19 Boot Control and Status 2 Register - 0x17
- 7.1.20 PCIE Switch Control and Status 1 Register - 0x18
- 7.1.21 PCIE Switch Control and Status 2 Register - 0x19
- 7.1.22 CPU Package Temperature Reading Register - 0x1C
- 7.1.23 IPMC Inlet Temperature Sensor Status Register - 0x1D
- 7.1.24 IPMC Outlet Temperature Sensor Status Register - 0x1E
- 7.1.25 FRAM Page Access Register - 0x20
- 7.1.26 VPX System Register - 0x24
- 7.1.27 POST Code Latch Register - 0x28
- 7.1.28 BIOS Boot Status Register - 0x2C
- 7.2 FPGA SIO
- 7.3 UART Register Overview
- 7.3.1 UART Registers DLAB=0
- 7.3.1.1 Received Buffer Register (RBR)
- 7.3.1.2 Transmitter Holding Register (THR)
- 7.3.1.3 Interrupt Enable Register (IER)
- 7.3.1.4 Interrupt Identification Register (IIR)
- 7.3.1.5 FIFO Control Register (FCR)
- 7.3.1.6 Line Control Register (LCR)
- 7.3.1.7 Modem Control Register (MCR)
- 7.3.1.8 Line Status Register (LSR)
- 7.3.1.9 Modem Status Register (MSR)
- 7.3.1.10 Scratch Register (SCR)
- 7.3.1.11 Programmable Baud Rate Generator
- 7.3.1 UART Registers DLAB=0
- 7.1 FPGA Registers
- A Related Documentation