Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 141)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 122
7.2.1.3 Configuration Mode
The system sets the logical device information and activates desired logical devices trough the
INDEX and DATA ports.
The desired configuration registers are accessed in two steps:
1. Write the index of the Logical Device Number Configuration Register (i.e., 07) to the INDEX
PORT and then write the number of the desired logical device to the DATA PORT.
2. Write the address of the desired configuration register within the logical device to the
INDEX PORT and then write or read the configuration register through the DATA PORT.
7.2.1.4 Super IO Configuration Registers
Address locations that are not listed are considered reserved register locations. Reads to
reserved registers may return non-zero values. Writes to reserved locations may cause system
failure.
7.2.1.5 Global Control Configuration Registers
The Super IO Global Registers lie in the address range 0x00-0x2F. All eight bits of the ADDRESS
Port are used for register selection. All unimplemented registers and bits ignore writes and
return zero when read. The INDEX PORT is used to select a configuration register in the chip.
The DATA PORT is then used to access the selected register. These registers are accessible only
in the Configuration Mode.
If accessing the Global Configuration Registers, Step 1 is not required. The Super IO returns to
the RUN State.
Only two states are defined (Run and Configuration). In the Run State the Super IO is always
ready to enter the Configuration State.
Table 7-31 Global Configuration Register Summary
Index Address Description
0x07 Super IO Logical Device Number
0x20 Super IO Device ID
0x21 Super IO Device Revision