Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 131)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 112
7.1.17 Misc 3 Control and Status Register - 0x15
Table 7-17 Misc 3 Control and Status Register - 0x15
Bit # Description Default LPC Access I2C Access
0 RTM Presence Status Ext. RO RO
0: RTM is not present.
1: RTM is present.
1 XMC ROOT0# 1 R/W RO
0: XMC root complex enabled.
1: XMC root complex disabled.
2 XMC MBIST# Ext. RO RO
0: XMC MBIST on-going.
1: XMC MBIST completed.
3 XMC WAKE# Ext. RO RO
0: XMC wake requested.
1: No wake request.
4 XMC PRSNT# Ext. RO RO
0: XMC is not present
1: No wake request
5 FPGA Control Registers Block Write Protect 0 R/W RO
0: Not write-protected
1: Write-protected
6 CPU PCIE Bifurcation Control 1 R/W RO
0: x8 x4 x4
1: x8 x8
7 Reserved 0 RO RO