Fpga registers – Artesyn iVPX7225 Installation and Use (April 2015) User Manual
Page 122
FPGA Registers
iVPX7225 Installation and Use (6806800S11C)
103
3
Reset due to IPMC reset request
0
R/WTC
RO
0: Reset not due to IPMC reset request.
1: Reset due to IPMC reset request.
4
Reset due to front panel push button switch
0
R/WTC
RO
0: Reset not due to front panel push button
switch.
1: Reset due to front panel push button switch.
5
Reset due to RTM front panel push button switch 0
R/WTC
RO
0: Reset not due to RTM front panel push button
switch.
1: Reset due to RTM front panel push button
switch.
6
Reset due to CPU Thermal Trip
0
R/WTC
RO
0: Reset not due to CPU Thermal trip signal.
1: Reset due to CPU Thermal trip signal.
7
Reset due to XDP DBR#
0
R/WTC
RO
0: Reset not due to XDP DBR#
1: Reset due to XDP DBR#
Table 7-7 FPGA Reset Cause Register - 0x08 (continued)
Bit #
Description
Default
LPC Access
I2C Access
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