Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 160)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 141
7.3.1.9 Modem Status Register (MSR)
This 8-bit register provides the current state of the control lines from the modem or data set
(or a peripheral device emulating a modem) to the processor. In addition to this current state
information, four bits of the Modem Status register provide change information. Bits 03:00 are
set to a logic 1 when a control input from the Modem changes state. They are reset to logic 0
when the processor reads the Modem Status register.
6 Transmitter Empty (TEMT) indicator
TEMT bit is set when the THR and the TSR are
both empty. When either the THR or the TSR
contains a data character, TEMT is cleared. In
the FIFO mode, TEMT is set when the
transmitter FIFO and shift register are both
empty:
1: THR/Transmit FIFO/TSR empty
0: THR/Transmit FIFO/TSR contains data 1 R
7 FIFO data error
In the FIFO mode, LSR7 is set when there is at
least one parity, framing, or break error in the
FIFO. It is cleared when the microprocessor
reads the LSR and there are no subsequent
errors in the FIFO. If FIFO is not used, bit always
reads 0:
1: FIFO data error encountered
0: No FIFO error encountered 0 R
Table 7-53 Line Status Register (LSR) (continued)
IO Address: Base +5
Bit # Description Default Access