Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 77)

Chapter 5
iVPX7225 Installation and Use (6806800S11C) 58
BIOS
5.1 Overview
The iVPX7225 BIOS is the primary firmware that controls initialization and functional tests on
all board components before hand over to the installed OS. It is based on the Phoenix
SecureCore Tiano Enhanced BIOS that follows the UEFI standard.
The BIOS is built upon the Chief River Platform (Ivy Bridge Processor and Panther Point 2-M
PCH) and is supplemented with the Intel ME firmware.
5.2 Processor Initialization
The processor has two physical cores with two logical cores on each physical core, totaling four
visible cores. Processor P2 will be selected as the BSP, and all four cores will be activated during
the DXE phase of BIOS.
Each core has a first level (L1) 32 KB instruction and 32 KB data cache and second level (L2) 256
KB shared instruction/data cache. There is a third level (L3) shared instruction/data cache with
up to 8 MB that is shared by all cores.
The BIOS enables the following processor features by default:
 Intel Hyper Threading (HT) Technology
 Dynamic Front Side Bus (FSB) Switching
 Execute Disable (XD) Bit
 Machine Check
 Intel SpeedStep
 Turbo Mode
 C-States
5.3 Memory Initialization
The iVPX-7225 has a total of 8 GB of physical main memory, where 3 GB is available in the lower
4GB (32-bit) address space for general use. The upper 1GB of 4GB address space is reserved for
systems tables and PCI address space. The BIOS sets the max TOLUD (Top of Lower Usable
DRAM) to 3 GB by default.